Associate Verification Engineer | RTL & System-Level Verification | SystemVerilog & UVM
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I will help you debug and improve your SystemVerilog or UVM-based verification environment. This service is useful for engineers or students who are facing issues with testbenches, sequences, drivers, monitors, or simulation failures. What's included: - Debugging SystemVerilog or UVM testbench issues - Guidance on verification architecture and methodology - Help understanding simulation failures or waveform analysis - Suggestions for improving testbench structure and coverage - Best practices for writing clean verification code Ideal for: - Students learning SystemVerilog/UVM - Engineers debugging verification environments - Teams needing quick verification guidance
I am an Associate Verification Engineer with experience in RTL and system-level verification of digital designs. I work on building verification environments, running tests, and debugging to ensure correct functionality. I have experience with SystemVerilog, UVM, and simulation tools, and I enjoy solving technical problems and working in team environments.